Conventionally, GPS receivers demodulate a signal modulated with a PN code to observe a carrier phase, a code phase, a navigation message and the like, which are used for positioning. As a method of demodulating the signal, initially, the received GPS signal is separated into an in-phase signal and a quadrature signal, which are in turn subjected to A/D conversion. Next, an in-phase signal and a quadrature signal in a base band are generated based on a carrier phase signal output from a carrier NCO. These signals and a PN code from a PN code generator are subjected to a correlation process, thereby reproducing information, such as a carrier phase, a code phase, a navigation message, and the like.
The GPS receiver comprises a code NCO as a code generator for generating a code enable signal which gives the PN code generator the timing of generating a PN code.
FIG. 18 is a block diagram schematically illustrating a configuration of a conventional general code NCO.
As illustrated in FIG. 18, the conventional code NCO comprises an adder 101, a multiplexer (MPX) 102, a register 103, and a latch circuit 104. The adder 101 receives a predetermined set value P, and an integer output from the register 103, and outputs the sum of these values to the multiplexer 102. The latch circuit 104 receives a phase adjustment value CPA (Code Phase Adjustment) for adjusting a phase of the code NCO, and a write enable signal WE, from a microprocessor (not shown), and outputs the phase adjustment value CPA with timing of the write enable signal WE. The multiplexer 102 receives the integer output from the adder 101 and the phase adjustment value CPA output from the latch circuit 104, and outputs either of them in accordance with an adjust timing signal AD (Adjust Timing). The register 103 latches and outputs a signal input from the multiplexer 102 to the adder 101 based on a sampling clock signal SCLK (hereinafter referred to as a “clock signal”), and also outputs the signal as a code enable signal.
In this case, a set value P is obtained by the following expression.
                    P        =                                            f              0                                      f              s                                ×                      2            L                                              (        1        )            
However, the set value P, which depends on the relationship between a frequency (fs) of the clock signal SCLK and a frequency fo of the code enable signal, is not always an integer. In this case, a so-called rounding error occurs, resulting in a reduction in code resolution of the code NCO or the occurrence of a cumulative error. Here, the resolution reduction can be overcome by increasing the number of bits of the adder or the register, and the occurrence of a cumulative error can be overcome by regularly inputting a phase adjustment value. However, this causes another problem, e.g., the circuit scale of the code NCO is increased, or the control is complicated.
An apparatus which solves such a problem is described in Patent Document 1. FIG. 19 is a block diagram schematically illustrating a configuration of the apparatus.
As illustrated in FIG. 19, a conventional code NCO having another configuration comprises a multiplexer 201, an adder 202, and a latch circuit 203.
The multiplexer 201 is operated either in a shift mode or in a normal mode.
In the shift mode, the multiplexer 201 receives and outputs a phase control value (CONTROL) to the adder 202. Here, the phase control value (CONTROL) is represented by the following expression, where L represents the number of bits of the adder 202 and the latch circuit 203.
                    CONTROL        =                              M            -            SHIFT                                              2              L                        -            M            +            N                                              (        2        )            
Here, SHIFT represents a phase amount by which the phase control value (CONTROL) is shifted from the current phase, in units of clock signals (SCLK).
In the normal mode, the multiplexer 201 selects and outputs an integer N or an integer M, depending on the value of Q12 of the latch circuit 203, which is input to a selector terminal (SELECT). Here, when Q12 is “0”, the integer N is output, and when Q12 is “1”, the integer M is output.
The adder 202 adds a value input from the multiplexer 201 and a value output from the latch circuit 203, and outputs the result to the latch circuit 203.
The latch circuit 203 latches the output from the adder 202 using the input clock signal SCLK. In this case, if Q12 is “1”, the output signal of the latch circuit 203 is externally output as a code enable signal CEC.
In the output of the thus-configured NCO, a frequency fo of the code enable signal CEC can be represented by the following expression.
                              f          0                =                              N            ×                          f              s                                                          2              L                        -            M            +            N                                              (        3        )            
The code NCO is optimally used under the following conditions.
The conditions are as follows: the frequency fs of the clock signal SCLK is 25 MHz, the number L of bits is 12, the integer N is 1023, and the integer M is 2619. In this case, the frequency fo of the code enable signal CEC is 10.23 MHz.
Patent Document 1: U.S. Pat. No. 5,663,733, Sep. 2, 1997